1. Field of the Invention
The present invention relates to semiconductor devices, a method of designing semiconductor devices, and recording media for storing semiconductor designing programs. In particular, the present invention relates to semiconductor devices having multilayer wiring structures, and a technique of designing a highly integrated semiconductor device having fine metal wires connected through via-contacts provided with extensions.
2. Description of the Related Art
Fine technology for semiconductor devices is rapidly improving to provide very small circuit patterns. The very small circuit patterns have a problem.
The problem is an optical proximity effect that occurs during a lithography process even if masks or stepper for producing circuit patterns are precise. The optical proximity effect rounds an end of a metal wire. If the rounded wire end is connected to a via-contact, it reduces or eliminates a contact area between the wire end and the via-contact, to increases contact resistance between the wire and the via-contact and cause an open defect.
FIG. 1 is a plan view showing a pattern of metal wires designed according to a prior art. Wires 53 and 54 are in an upper layer and are connected to via-contacts 51 and 52, respectively. The via-contacts 51 and 52 are connected to wires 55 and 56 that are in a lower layer. FIG. 2 is a plan view showing metal wires manufactured according to the design of FIG. 1. FIG. 3 is a sectional view taken along a grid line V2 of FIG. 2. In FIGS. 1 and 2, the distance between adjacent grid lines indicates a minimum distance by which adjacent metal wires in each layer must be separated from each other. In FIG. 1, an end of each wire is square and is in contact with the whole surface of a via-contact. A mask formed according to the design of FIG. 1 also has a square shape for each wire end. During a lithography process, however, the optical proximity effect rounds each end of the wires 53 and 54 as shown in FIG. 2. The optical proximity effect may make the ends of the wires 53 and 54 recede in the arrow directions of FIG. 3, to reduce contact areas between the wires 53 and 54 and the via-contacts 51 and 52. In FIG. 3, dotted lines indicate designed ends of the wires 53 and 54.
There is an OPC (optical proximity correction) technique to increase a contact area between a metal wire end and a via-contact. This technique corrects wire ends when preparing data to make a mask. For example, this technique provides a wire end with a supplementary fringe that extends in every direction around a via-contact. FIG. 4 shows a pattern of metal wires having supplementary fringes 58 and 59 to cover via-contacts 51 and 52 according to a prior art. The pattern of FIG. 4 is useful to form metal wires having no round ends and having proper contact areas between the wire ends and via-contacts.
The supplementary fringes 58 and 59, however, increase the width of each wire at each via-contact greater than the width of the other part of the wire. It is necessary, therefore, to separate the adjacent via-contacts 51 and 52 from each other with a grid line H2 interposing between them. In addition, other wires or via-contacts must not be arranged on grid lines that are adjacent to the via-contacts 51 and 52, or the intervals of grid lines must be increased to accommodate the supplementary fringes 58 and 59. These conditions deteriorate the integration of metal wires in a semiconductor device.
The supplementary fringes also increase the quantity of design data, extend a mask data preparation time, and elongate a semiconductor device development time.
An object of the present invention is to provide a semiconductor device that is highly integrated and minimizes contact defects between metal wires and via-contacts, a method of designing such a semiconductor device, and a recording medium storing a program for designing such a semiconductor device.
Another object of the present invention is to provide a semiconductor device involving a short development time, a method of designing such a semiconductor device, and a recording medium storing a program for designing such a semiconductor device.
In order to accomplish the objects, a first aspect of the present invention provides a semiconductor device having a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire.
The xe2x80x9cvia-contactxe2x80x9d is a conductive plug formed in an intermediate layer between wiring layers in a semiconductor device of multilayer wiring structure, to electrically connect metal wires of the upper and lower wiring layers to each other. The via-contact may have any plan shape, such as a quadrate or a circle. The xe2x80x9cmain wirexe2x80x9d is a metal wire to electrically connect functional blocks, elements, or external terminals on a semiconductor chip. The xe2x80x9cextensionxe2x80x9d is a metal wire extended from an end of the main wire and electrically connected thereto. It is preferable that the extension is equal to the main wire in materials, manufacturing methods, and manufacturing processes. The extension extends in line with the main wire, i.e., in the length direction of the main wire and runs over the via-contact, unlike the supplementary fringe of the prior art that extends in all dictions around a via-contact. The extension may have any plan shape, such as a quadrate or a circle.
According to the first aspect, the extension is extended in line with the main wire from an end of the main wire beyond the via-contact with the width of the extension being equal to or narrower than the width of the main wire. The optical proximity effect rounds only an end of the extension, and therefore, the end of the main wire is intact and is properly connected to the via-contact without bulging around the via-contact. As a result, other main wires or via-contacts may be arranged on grid lines or on grid intersections in the vicinity of the via-contact in question without violating design rules. This realizes a highly integrated layout for a semiconductor device with densely arranged wires and via-contacts.
A second aspect of the present invention provides a semiconductor device having a via-contact, a main wire having an end connected to the via-contact, and an extension orthogonally extended from the end of the main wire beyond the via contact, the width of the extension being equal to or narrower than the width of the main wire.
According to the second aspect, the extension is orthogonally extended from an end of the main wire beyond the via-contact with the width of the extension being equal to or narrower than the width of the main wire. The optical proximity effect rounds only ends of the extension, and therefore, the end of the main wire is intact and is properly connected to the via-contact.
A third aspect of the present invention provides a method of designing a semiconductor device having X wiring layers. The method includes the steps of arranging functional blocks and elements in a chip area with the use of an automatic layout tool, and arranging main wires in a layer N, main wires in a layer N+1, and via-contacts in the layer N with the use of the automatic layout tool, to connect the functional blocks and elements to one another through the main wires and via-contacts. The via-contacts in the layer N include:
(1) the via-contacts themselves to electrically connect the main wires in the layer N to the main wires in the layer N+1;
(2) an extension formed in the layer N+1 on and beyond each of the via-contacts and extended from an end of a corresponding one of the main wires of the layer N+1 in line with the main wire, the width of the extension being equal to or narrower than the width of the main wire; and
(3) an extension formed in the layer N under and beyond each of the via-contacts and extended from an end of a corresponding one of the main wires of the layer N in line with the main wire, the width of the extension being equal to or narrower than the width of the main wire.
Here, X is a natural number and N is a natural number satisfying 0 less than =N less than =Xxe2x88x921. If N=0 then a wiring layer N is a substrate, and a wiring layer N+1 is a first wiring layer. It is preferable that all via-contacts in the wiring layers have the same characteristics as those mentioned above. Even if a designer provides the via-contacts of the above characteristics only for specific wiring layers of a semiconductor device, the effect of the present invention will be demonstrated in the semiconductor device. xe2x80x9cIn line withxe2x80x9d means that the extension has placed for wiring direction only in 0 degree direction and 180 degree direction.
According to the third aspect, each via-contact has extensions each connected to an end of a main wire. The optical proximity effect rounds only the extensions, and therefore, the end of each main wire is intact and is properly connected to the via-contact. An end of each main wire is not widened around a via-contact, so that other main wires or via-contacts may be arranged on grid lines or on grid intersections in the vicinity of the via-contact in question without violating design rules. This realizes a highly integrated layout for a semiconductor device with densely arranged wires and via-contacts. Data for via-contacts entered into an automatic layout tool may include data for the extensions, so that there is no necessity to provide a main wire with the extension as a supplementary fringe when preparing data to make a mask. This decreases the quantity of design pattern data, shortens a mask data preparation time, and reduces a semiconductor device development time.
A fourth aspect of the present invention provides a method of designing a semiconductor device having X wiring layers. The method includes the steps of arranging functional blocks and elements in a chip area with the use of an automatic layout tool, and arranging main wires in a layer N, main wires in a layer N+1, and via-contacts in the layer N with the use of the automatic layout tool, to connect the functional blocks and elements to one another through the main wires and via-contacts. The via-contacts in the layer N include:
(1) the via-contacts themselves to electrically connect the main wires in the layer N to the main wires in the layer N+1;
(2) an extension formed in the layer N+1 on and beyond each of the via-contacts in contact with an end of a corresponding one of the main wires of the layer N+1 and extended orthogonally to the main wire, the width of the extension being equal to or narrower than the width of the main wire; and
(3) an extension formed in the layer N under and beyond each of the via-contacts in contact with an end of a corresponding one of the main wires of the layer N and extended orthogonally to the main wire, the width of the extension being equal to or narrower than the width of the main wire. xe2x80x9cOrthogonally toxe2x80x9d means that the extension has placed for wiring direction only in 90 degree direction and 270 degree direction.
According to the fourth aspect, each via-contact has extensions each connected to an end of a main wire. The optical proximity effect rounds only the extensions, and therefore, the end of each main wire is intact and is properly connected to the via-contact. Data for via-contacts entered into an automatic layout tool may include data for the extensions, so that there is no necessity to provide a main wire with the extension as a supplementary fringe when preparing data to make a mask. This decreases the quantity of design pattern data, shortens a mask data preparation time, and reduces a semiconductor device development time.
A fifth aspect of the present invention provides a recording medium for storing a program that is used to design a semiconductor device having X wiring layers. The program includes the steps of arranging functional blocks and elements in a chip area with the use of an automatic layout tool, and arranging main wires in a layer N, main wires in a layer N+1, and via-contacts in the layer N with the use of the automatic layout tool, to connect the functional blocks and elements to one another through the main wires and via-contacts. The via-contacts in the layer N include:
(1) the via-contacts themselves to electrically connect the main wires in the layer N to the main wires in the layer N+1;
(2) an extension formed in the layer N+1 on and beyond each of the via-contacts and extended from an end of a corresponding one of the main wires of the layer N+1 in line with the main wire, the width of the extension being equal to or narrower than the width of the main wire; and
(3) an extension formed in the layer N under and beyond each of the via-contacts and extended from an end of a corresponding one of the main wires of the layer N in line with the main wire, the width of the extension being equal to or narrower than the width of the main wire.
A sixth aspect of the present invention provides a recording medium for storing a program that is used to design a semiconductor device having X wiring layers. The program includes the steps of arranging functional blocks and elements on a chip with the use of an automatic layout tool, and arranging main wires in a layer N, main wires in a layer N+1, and via-contacts in the layer N with the use of the automatic layout tool, to connect the functional blocks and elements to one another through the main wires and via-contacts. The via-contacts in the layer N include:
(1) the via-contacts themselves to electrically connect the main wires in the layer N to the main wires in the layer N+1;
(2) an extension formed in the layer N+1 on and beyond each of the via-contacts in contact with an end of a corresponding one of the main wires of the layer N+1 and extended orthogonally to the main wire, the width of the extension being equal to or narrower than the width of the main wire; and
(3) an extension formed in the layer N under and beyond each of the via-contacts in contact with an end of a corresponding one of the main wires of the layer N and extended orthogonally to the main wire, the width of the extension being equal to or narrower than the width of the main wire.
Other and further objects and features of the present invention will become obvious upon an understanding of the illustrative embodiments about to be described in connection with the accompanying drawings or will be indicated in the appended claims, and various advantages not referred to herein will occur to one skilled in the art upon employing of the invention in practice.